1. Field of the Invention
The present invention relates to a sample and hold circuit and more particularly to the sample and hold circuit which is used for sampling a video signal in an integrated circuit for driving active matrix liquid crystal.
2. Description of the Related Art
Before describing the sample and hold circuit known by the inventors of the present application, the driving circuit for liquid crystal with which the sample and hold circuit of this invention concerns will be described. Such a driving circuit is typically arranged to have a plurality of-signal electrodes located in parallel, a plurality of scan electrodes crossed with those signal electrodes, pixel electrodes provided near each of the cross points between the signal electrodes and the scan electrodes, opposite electrodes located in opposition to the pixel electrodes, and auxiliary capacitance electrodes located in a manner to form capacitances with the pixel electrodes. The later description will be expanded as taking an example of an active matrix liquid crystal display unit. However, it goes without saying that this invention is applicable to an electroluminescent display unit and a plasma display unit.
FIG. 1 exemplarily shows the known active matrix liquid crystal display unit. As shown, this display unit provides a TFT (Thin Film Transistor) liquid crystal panel 100 having TFTs 104 served as switching elements for driving the pixel electrodes 103 arranged in a matrix manner. The TFT liquid crystal panel 100 includes a plurality of scan electrodes 101 located in parallel to one another and a plurality of signal electrodes 102 crossed with and located in parallel to the scan electrodes 101. The TFT 104 for driving the pixel electrode 103 is provided closer to each cross point between the scan electrode 101 and the signal electrode 102. Opposite electrodes 105 are provided as opposed to the pixel electrodes 103, respectively. The opposite electrode 105 is exemplarily shown in FIG. 1. Normally, however, it is composed of one conductive layer commonly located to all the pixel electrodes 103. A certain amount of voltage Ve is applied to the opposite electrode 105. The TFT liquid crystal panel 100 further includes a plurality of auxiliary capacitance electrodes 106, which will be discussed later.
The TFT liquid crystal panel 100 is driven by a driving circuit including a source driver 200 and a gate driver 300. The source driver 200 is connected to the signal electrodes 102 of the TFT panel 100. The gate driver 300 is connected to the scan electrodes 101 of the TFT panel 100. The source driver 200 operates to sample and hold an analog image signal or a video signal input thereto and then feed it to the signal electrodes 102. The gate driver 300 operates to sequentially output a scan pulse to the scan electrodes 101. Various control signals such as a timing signal input to the gate driver 800 and the source driver 200 are fed from a control circuit 400.
Then, the source driver 200 will be discussed in detail as referring to FIG. 2. The source driver 200 includes a shift register 210, a sample and hold circuit 220 and an output buffer 280. The shift register 210 operates to shift a shift pulse input from the control circuit 800 on the shift clocks and sequentially output a sampling pulse to the lines B1, B2 . . . Bi . . . Bm on shift clocks. Based on the sampling pulse, the analog switches ASWI(1) . . . ASWi(i) . . . ASWi(m) in [he sample and hold circuit 220 are sequentially made conductive. The sampling capacitor 221 is charged up to the same level as the instantaneous amplitude v(i, j) of the input analog image signal. Herein, v(i, j) denotes an instantaneous amplitude of an analog image signal to be written in the pixel electrode 103 corresponding to a cross point between the i-th signal electrode and the j-th scan electrode. After the sample and hold circuit 220 takes sampling of an image signal for one horizontal scan period, an output pulse OE is applied to the source driver so that the image signal is shifted from the sampling capacitor 221 to the holding capacitor 222. The image signal held in the holding capacitor 222 is output to the signal electrode 102 through the output buffer 230.
FIG. 3 schematically shows a waveform of an I/O signal in the source driver 200. In FIG. 8, v(CSPL(i)), v(CH(i)) and Vs(i) denote a voltage in the i-th sampling capacitor 221, a voltage in the i-th holding capacitor 222 and an output voltage of the i-th output buffer 230, respectively. As shown in FIG. 3, the signal electrode 102 is normally driven by an ac voltage in a manner that the polarity of the applied voltage against the voltage applied on the opposite electrode 105 in one field is different from that in the adjacent field.
FIG. 4 shows an equivalent circuit of a pixel. As shown in FIG. 4, in addition to a pixel capacitance CLC formed between the pixel electrode 103 and the opposite electrode 105, an auxiliary capacitance Cs is formed between the pixel electrode 103 and the auxiliary capacitance electrode 106. In the TFT liquid crystal panel 100, even if the signal electrode 102 is ac driven, an ac waveform applied to the liquid crystal element is made asynchronous. A polarized electric field due to the asynchrony is formed in the liquid crystal element. This polarized electric field leads to lowering the reliability of the liquid crystal element. The addition of the auxiliary capacitance Cs is intended for improving such a disadvantage and reducing a flicker phenomenon. The pixel electrode 103 serves as one electrode of the auxiliary capacitance Cs. As the other electrode of the auxiliary capacitance Cs, that is, the connecting system of the auxiliary capacitance electrode 106, the following two systems are known.
In the first system, as shown in FIG. 1, the auxiliary capacitance electrode 106 corresponding to the j-th scan electrode 101 is electrically connected to the adjacent (j-l) th scan electrode 101. However, the auxiliary capacitance electrode 106 corresponding to the (j=0) th scan electrode 101 is connected to the opposite electrode 105. This system is referred to as a Cs on-gate system.
In the second system, as shown in FIG. 5, the auxiliary capacitance electrode 106 is electrically connected to the opposite electrode 105. In this case, the voltage vx of the auxiliary capacitance electrode 106 is equal to the voltage vc of the opposite electrode 105.
In the second system, it is necessary to wire a pick-up bus line for connecting the auxiliary capacitance electrode 106 to the opposite electrode 105 in parallel to the scan electrode. This results in bringing about the disadvantage of lowering a numerical aperture. On the other hand, since the gate electrode serves as the pick-up bus line, the first system is more advantageous in light of the numerical aperture.
The known source driver is arranged of a logic circuit such as a counter and a shift register operated on a low voltage, and a middle voltage endurance section such as a sample and hold circuit, a level shifter circuit, and an output buffer. To manufacture the part operating on different voltages as a monolithic LSI, it is necessary to employ a design rule and a manufacture process suited to the middle voltage endurance section.
FIG. 6 shows a sample and hold circuit known by the inventors of the present applicant. The timing of the known sample and hold circuit is shown in FIG. 7. It is basically equal to the timing of the present invention.
The known sample and hold circuit operates to sequentially switch on and off the analog switch Gn on the timing of an output signal Qn of a shift register 2 and take sampling of the data in the corresponding capacitor Cn for holding an analog signal Vi input to an input bus line 1 for a certain interval.
Consider the case that the analog switch is continuously switched on and off in the known circuit. Since the trailing edge of the n-th sampling gate signal is the same timing as the leading edge of the (n+1) th sampling gate signal, the (n+1) th gate is switched on before the n-th gate Gn is completely switched off because the waveform of this gate signal is transformed or delayed. If the-sampling gate as shown in FIG. 6 is composed of an analog switch made of P-MOS and N-MOS, it is known that the adjacent gates remain on at the same time for a longer interval of time.
On the other hand, when the sampling gate Gn+1 is switched on, the charge or discharge of the capacitance Cn+1 may give an adverse effect to the input bus line as noises in some histories of the voltage level accumulated in the sampling capacitance Cn+1. Hence, the sampling capacitance Cn does not disadvantageously reach the necessary input level.